M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 112

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
9.7 NMI Interrupt
9.8 Key Input Interrupt
e
E
1
. v
J
Figure 9.12 Key Input Interrupt
6
0
_______
_______
An NMI interrupt request is generated when input on the NMI pin changes state from high to low, after the
NMI interrupt was enabled by writing a 1 to bit 4 in the register PM2. The NMI interrupt is a non-maskable
interrupt, once it is enabled.
The input level of this NMI interrupt input pin can be read by accessing the P8_5 bit in the P8 register.
NMI is disabled by default after reset (the pin is a GPIO pin, P8
register. Once enabled, it can only be disabled by a reset signal.
The NMI input has a digital debounce function for noise rejection. Refer to "19.6 Digital Debounce func-
tion" for details. When using NMI interrupt to exit stop mode, set the NDDR register to FF
stop mode.
A key input interrupt is generated when input on any of the P10
PD10_4 in the PD10 register set to 0 (= input) goes low. Key input interrupts can be used for a key-on
wakeup function to get the MCU to exit stop or wait modes. However, if you intend to use the key input
interrupt, do not use P10
input interrupt. Note, however, that while input on any pin which has had bits PD10_7 to PD10_4 set to 0 (=
input mode) is pulled low, inputs on all other pins of the port are not detected as interrupts.
C
1
9
1 .
______
B
2 /
0
2
_______
9
1
_______
Pull-up
transistor
M
0
G
1
r a
0 -
o r
KI
KI
3 .
KI
KI
1
u
3
2
1
0
, 0
1
p
2
2
0
Pull-up
transistor
Pull-up
transistor
0
Pull-up
transistor
7
page 86
_______
4
to P10
PD10_5 bit in the
PD10 register
PD10_4 bit in the
PD10 register
PD10_6 bit in the
PD10 register
PD10_7 bit in the PD10 register
_______
f o
4
7
5
8
as analog input ports. Figure 9.12 shows the block diagram of the key
PU25 bit in the PUR2
register
PD10_7 bit in the
PD10 register
_______
5
4
) and can be enabled using bit 4 in the PM2
to P10
Interrupt control circuit
KUPIC register
7
pins which has had bits PD10_7 to
______
Key input interrupt
request
16
before entering