M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 336

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
1
. v
Figure 17.25 Timing of Receive Data Frame Sequence
J
6
0
17.10.1 Reception
C
1
9
Reception Interrupt
j = 0 to 15
1 .
(1) On monitoring a SOF on the CAN bus the RecState bit in the C0STR register becomes 1 (CAN module
(2) After successful reception of the message, the NewData bit in the C0MCTLj register (j = 0 to 15) of the
(3) When the interrupt enable bit in the C0ICR register of the receiving slot = 1 (interrupt enabled), the
(4) Read the message out of the slot after setting the New Data bit to 0 (the content of the slot is read or
(5) If the NewData bit is set to 0 by program or the next CAN message is received successfully before the
B
Figure 17.25 shows the behavior of the module when receiving two consecutive CAN messages, that fit
into the slot of the shown C0MCTLj register (j = 0 to 15) and leads to losing/overwriting of the first
message.
2 /
CAN0 Successful
0
2
9
1
is receiver) immediately, given the module has no transmission pending.
receiving slot becomes 1 (stored new data in slot). The InvalData bit in the C0MCTLj register
becomes 1 (message is being updated) at the same time and the InvalData bit becomes 0 (message is
valid) again after the complete message was transferred to the slot.
CAN0 successful reception interrupt request is generated and the MBOX bit in the C0STR register is
changed. It shows the slot number where the message was stored and the RecSucc bit in the
C0STR register is active.
still under processing by the CPU) by program.
receive request for the slot is canceled, the MsgLost bit in the C0MCTLj register is set to 1 (message
has been overwritten). The new received message is transferred to the slot. Generating of an
interrupt request and change of the C0STR register are same as in 3).
M
0
G
InvalData bit
NewData bit
RecState bit
RecSucc bit
1
r a
MsgLost bit
RecReq bit
0 -
o r
MBOX bit
3 .
CANbus
1
u
, 0
1
p
2
2
0
0
7
page 310
SOF
(1)
f o
4
5
8
ACK
EOF
(2)
(2)
(3)
IFS
SOF
Receive slot No.
(4)
ACK
EOF
(5)
(5)
(5)
IFS