M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 222

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
1
. v
J
NOTES:
6
Table 14.10 I
0
14.1.3 Special Mode 1 (I
Interrupt request
generation timing
C
Transfer data format
Transfer clock
Transmission start condition
Reception start condition
Error detection
Select function
1
9
1 .
B
2 /
I
specifications of the I
and the register values set. Table 14.13 lists the I
diagram for I
As shown in Table 14.13, the MCU is placed in I
the IICM bit to 1. Because SDA
change state until SCL
1. When an external clock is selected, the conditions must be met while the external clock is in the high
2. If an overrun error occurs, bits 8 to 0 in the U2RB register are undefined. The IR bit in the S2RIC
2
0
2
C bus mode is provided for use as a simplifed I
9
1
M
state.
register remains unchange.
0
G
1
r a
o r
0 -
3 .
1
u
Item
, 0
1
p
2
2
2
0
C bus mode Specifications
2
0
C bus mode. Figure 14.23 shows SCL
7
page 196
2
C bus mode. Tables 14.11 and 14.12 list the registers used in the I
2
goes low and remains stably low.
• Transfer data length: 8 bits
• During master
• During slave
• Before transmission can start, the following requirements must be met
_
_
• Before reception can start, the following requirements must be met
_
_
_
When start or stop condition is detected, acknowledge undetected, and acknowledge
detected
• Overrun error
• Arbitration lost
• SDA digital delay
• Clock phase setting
the CKDIR bit in the U2MR register is set to 0 (internal clock) : fj/ (2(n+1))
fj = f
CKDIR bit is set to 1 (external clock ) : Input from SCL
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the 8th bit in the the next data
Timing at which the ABT bit in the U2RB register is updated can be selected
No digital delay or a delay of 2 to 8 U2BRG count source clock cycles selectable
With or without clock delay selectable
The TE bit in the U2C1 register is set to 1 (transmission enabled)
The TI bit in the U2C1 register is set to 0 (data present in U2TB register)
The RE bit in the U2C1 register is set to 1 (reception enabled)
The TE bit in the U2C1 register is set to 1 (transmission enabled)
The TI bit in the U2C1 register is set to 0 (data present in the UiTB register)
f o
2
C bus mode)(UART2)
4
1SIO
5
8
2
, f
transmit output has a delay circuit attached, SDA output does not
2SIO
(2)
, f
8SIO
, f
32SIO
2
2
C bus mode by setting bits SMD2 to SMD0 to 010
C bus interface compatible mode. Table 14.10 lists the
2
C bus mode fuctions. Figure 14.22 shows the block
. n: Setting value in the U2BRG register 00
2
timing.
Specification
2
pin
(1)
2
(1)
C bus mode
16
to FF
2
16
and