M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 452

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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22.4 Interrupts
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E
1
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J
6
0
22.4.1 Reading Address 00000
22.4.2 Setting the SP
22.4.3 NMI Interrupt
22.4.4 Changing the Interrupt Generate Factor
C
1
9
1 .
B
2 /
Do not read the address 00000
reads interrupt information (interrupt number and interrupt request priority level) from the address
00000
If the address 00000
among the enabled interrupts is cleared to 0. This causes a problem that the interrupt is canceled, or an
unexpected interrupt request is generated.
Set any value in the SP(USP, ISP) before accepting an interrupt. The SP(USP, ISP) is cleared to 0000
after reset. Therefore, if an interrupt is accepted before setting any value in the SP(USP, ISP), the pro-
gram may go out of control.
1. The NMI interrupt is invalid after reset. The NMI interrupt becomes effective by setting the PM24 bit in
2. The input level of the NMI pin can be read by accessing the P8_5 bit in the P8 register.
3. When selecting NMI function, stop mode cannot be entered into while input on the NMI pin is low. This
4. When selecting NMI function, do not go to wait mode while input on the NMI pin is low. This is because
5. When selecting NMI function, the low and high level durations of the input signal to the NMI pin must
6. When using the NMI interrupt for exiting stop mode, set the NDDR register to FF
If the interrupt generate factor is changed, the IR bit in the interrupt control register for the changed
interrupt may inadvertently be set to 1 (interrupt requested). If you changed the interrupt generate factor
for an interrupt that needs to be used, be sure to clear the IR bit for that interrupt to 0 (interrupt not
requested).
“Changing the interrupt generate factor” referred to here means any act of changing the source, polarity
or timing of the interrupt assigned to each software interrupt number. Therefore, if a mode change of any
peripheral function involves changing the generate factor, polarity or timing of an interrupt, be sure to
clear the IR bit for that interrupt to 0 (interrupt not requested) after making such changes. Refer to the
description of each peripheral function for details about the interrupts from peripheral functions.
Figure 22.2 shows the procedure for changing the interrupt generate factor.
0
2
the PM2 register to “1”. Set the PM24 bit to "1" when a high-level signal ("H") is applied to the NMI pin.
If the PM24 bit is set to "1" when a low-level signal ("L") is applied, NMI interrupt is generated. Once NMI
interrupt is enabled, it will not be disabled unless a reset is applied.
is because while input on the NMI pin is low the CM1 register’s CM10 bit is fixed to 0.
when input on the NMI pin goes low, the CPU stops but CPU clock remains active; therefore, the current
consumption in the chip does not drop. In this case, normal condition is restored by an interrupt gener-
ated thereafter.
each be 2 CPU clock cycles + 300 ns or more.
debounce filter) before entering stop mode.
9
1
M
0
G
1
r a
o r
0 -
16
3 .
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u
, 0
1
p
during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to 0.
2
2
0
0
7
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is read in a program, the IR bit for the interrupt which has the highest priority
f o
4
16
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5
8
in a program. When a maskable interrupt request is accepted, the CPU
16
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16
(disable digital
22. Usage Notes
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