M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 108

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
1
. v
J
Figure 9.8 Operation of Saving Register
6
0
C
1
9
1 .
B
The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP
at the time of acceptance of an interrupt request, is even or odd. If the stack pointer
register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time.
Figure 9.8 shows the operation of the saving registers.
NOTE:
2 /
0
2
9
1
M
1. When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated
0
G
1
r a
0 -
o r
by the U flag. Otherwise, it is the ISP.
3 .
1
u
, 0
1
p
2
2
0
0
7
NOTE:
(1) SP contains even number
[SP] – 5 (Odd)
[SP] – 4 (Even)
[SP] – 3 (Odd)
[SP] – 2 (Even)
[SP] – 1 (Odd)
[SP]
(2) SP contains odd number
[SP] – 5 (Even)
[SP] – 4 (Odd)
[SP] – 3 (Even)
[SP] – 2 (Odd)
[SP] – 1 (Even)
[SP]
page 82
1. [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Address
Address
(Odd)
(Even)
f o
4
5
8
FLG
FLG
Stack
Stack
H
H
FLG
FLG
PC
PC
PC
PC
M
M
L
L
L
L
PC
PC
H
H
Sequence in which order
registers are saved
Sequence in which order
registers are saved
Finished saving registers
in two operations.
(3)
(4)
(1)
(2)
(2) Saved simultaneously,
(1) Saved simultaneously,
Finished saving registers
in four operations.
all 16 bits
all 16 bits
Saved, 8 bits at a time
(1)
is even, the FLG
(1)
,