M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 309

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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1
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16.13.2 Example of Slave Receive
1
9
C
1 .
B
For example, a slave receives data as shown below when following conditions are met: high-speed clock
mode, SCL frequency of 400 kHz, ACK clock added and addressing format.
2 /
0
2
9
1
M
0
1) Set a slave address in the 7 high-order bits in the S0D0 register
2) Set A5
3) Set 00
4) Set 08
5) When a START condition is received, addresses are compared
6) •When the transmitted addresses are all 0 (general call), the ADR0 bit in the S10 register is set to 1
7) Write dummy data to the S00 register.
8) After receiving 1-byte data, an ACK-CLK bit is automatically returned and an I
9) To determine whether the ACK should be returned depending on contents in the received data, set
10) When receiving more than 1-byte control data, repeat steps 7) and 8) or 7) and 9).
11) When a STOP condition is detected, the communication is ended.
G
1
r a
0 -
o r
•When the transmitted addresses match with the address set in 1), the ASS bit in the S10 register
•In other cases, bits ADR0 and AAS are set to 0 and I
3 .
register to generate an ACK clock and set SCL clock frequency at 400kHz (f
interrupt request signal is generated.
dummy data to the S00 register to receive data after setting the WIT bit in te S3D0 register to 1
(enable the I
interrupt is generated when the 1-byte data is received, set the ACKBIT bit to 1 or 0 to output a
signal from the ACKBIT bit.
and an I
1
is set to 1 and an I
generated.
u
, 0
1
p
2
2
0
0
16
16
16
7
2
to the S10 register to reset transmit/receive mode
to the S1D0 register to enable data communication
to the S20 register, 000
C bus interface interrupt request signal is generated.
page 283
2
C bus interface interrupt of data receive completion). Because the I
2
C bus interface interrupt request signal is generated.
f o
4
5
8
2
to bits ICK4 to ICK2 in the S4D0 register, and 00
2
C bus interface interrupt request signal is not
1
= 8 MHz, f
2
2
C bus interface
C bus interface
16
to the S3D0
IIC
= f
1
)