M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 91

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
1
. v
J
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
6
Table 7.7 Allowed Transition and Setting
NOTES:
0
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
1
C
9
9. ( ) : setting method. Refer to following table.
1. Avoid making a transition when the CM20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled).
2. On-chip oscillator clock oscillates and stops in low-speed mode. In this mode, the on-chip oscillator can be used as peripheral function clock.
3. PLL operation mode can only be entered from and changed to high-speed mode.
4. Set the CM06 bit to 1 (division by 8 mode) before transiting from on-chip oscillator mode to high- or middle-speed mode.
5. When exiting stop mode, the CM06 bit is set to 1 (division by 8 mode).
6. If the CM05 bit is set to 1 (main clock stop), then the CM06 bit is set to 1 (division by 8 mode).
7. A transition can be made only when sub clock is oscillating.
8. State transitions within the same mode (divide-by-n values changed or subclock oscillation turned on or off) are shown in the table below.
1 .
B
No division
Divided by 2
Divided by 4
Divided by 8
Divided by 16
No division
Divided by 2
Divided by 4
Divided by 8
Divided by 16
2 /
Set the CM20 bit to 0 (oscillation stop, re-oscillation detection function disabled) before transiting.
Sub clock oscillates and stops in PLL operation mode. In this mode, sub clock can be used as a clock for the timers A and B.
0
2
CM17 = 0 , CM16 = 0
CM17 = 0 , CM16 = 1
CM17 = 1 , CM16 = 0
CM17 = 1 , CM16 = 1
9
Hardware interrupt
1
wait instruction
M
0
CM06 = 0,
Low-speed mode 2
Low power dissipation
mode
PLL operation mode 2
On-chip oscillator mode
Stop mode
Wait mode
CM06 = 0,
G
PLC07 = 0,
PLC07 = 1,
On-chip oscillator
low power dissipation
mode
Setting
CM04 = 0
CM04 = 1
CM06 = 0,
CM06 = 0,
CM06 = 1
CM07 = 0
CM07 = 1
CM05 = 0
CM05 = 1
CM11 = 0
CM11 = 1
CM21 = 0
CM21 = 1
CM10 = 1
High-speed mode,
middle-speed mode
1
r a
0 -
o r
3 .
1
No
division
u
, 0
(3)
(3)
(3)
(3)
(2)
1
--
--
--
--
p
2
2
0
0
Divided
by 2
(4)
(4)
(4)
(4)
Sub clock turned off
Sub clock oscillating
CPU clock division by 2 mode
CPU clock division by 4 mode
CPU clock division by 16 mode
CPU clock division by 8 mode
Sub clock selected
Main clock oscillating
Main clock turned off
Main clock selected
PLL clock selected
Main clock or PLL clock selected
On-chip oscillator clock selected
Transition to stop mode
Transition to wait mode
Exit stop mode or wait mode
(2)
CPU clock no division mode
Main clock, PLL clock,
or on-chip oscillator clock selected
7
--
--
--
--
Sub clock oscillating
High-speed mode,
middle-speed mode
Divided
by 4
(5)
(5)
(5)
(5)
(2)
--
--
--
--
page 65
(12) 3
(14) 4
(18) 5
(18)
(8)
8
--
--
Operation
Divided
by 8
(7)
(7)
(7)
(7)
(2)
--
--
--
--
Low-speed mode 2
f o
Divided
by 16
(6)
(6)
(6)
(6)
(2)
--
--
--
--
4
(18)
(10)
(18)
(9) 7
5
(9) 7
--
--
8
No
division
(1)
(3)
(3)
(3)
(3)
--
--
--
--
Low power
dissipation mode
Divided
by 2
(1)
(4)
(4)
(4)
(4)
--
--
--
--
(11) 1, 6
(18)
(18)
--
--
--
--
Sub clock turned off
CM04, CM05, CM06, CM07 : Bits in the CM0 register
CM10, CM11, CM16, CM17 : Bits in the CM1 register
CM20, CM21
PLC07
Divided
by 4
(1)
(5)
(5)
(5)
(5)
--
--
--
--
PLL operation
mode 2
Divided
by 8
--: Cannot transit
(1)
(7)
(7)
(7)
(7)
--
--
--
--
(13) 3
State after transition
--
--
--
--
--
--
Divided
by 16
(1)
(6)
(6)
(6)
(6)
--
--
--
--
: Bits in the CM2 register
: Bit in the PLC0 register
On-chip oscillator
mode
(15)
(10)
(18) 5
(18)
(8)
--
--
8
On-chip oscillator
low power
dissipation mode
(11) 1
(18) 5
(18)
--
--
--
--
8
Stop mode
(16) 1
(16) 1
(16) 1
(16) 1
(16) 1
--
--
--: Cannot transit
Wait mode
(17)
(17)
(17)
(17)
(17)
--
--