M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 79

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
1
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Figure 7.7 PLC0 Register and CCLKR register
6
0
1
C
9
1 .
B
2 /
0
2
9
1
M
0
G
1
r a
NOTES:
CAN0 Clock Select Register
0 -
o r
NOTES:
b7
3 .
1. Write to this register after setting the PRC0 bit in the PRCR register to 1 (write enable).
2. Configuration of bits CCLK2 to CCLK0 can be done only when the Reset bit in the C0CTLR register is set to 1
3. Before setting this bit to 1(CAN0 CPU interface in sleep), set the Sleep bit in C0CTLR register to 1 (Sleep
1
u
PLL Control Register 0
, 0
1. Write to this register after setting the PRC0 bit in the PRCR register to 1 (write enable).
2. When the PM21 bit in the PM2 register is 1 (clock modification disable), writing to this register has no effect.
3. These three bits can only be modified when the PLC07 bit is set to 0 (PLL turned off). The value once written to
4. Before setting this bit to 1 , set the CM07 bit to 0 (main clock), set bits CM17 to CM16 bits to 00
1
b7
p
b6
(Reset/Initialization mode).
mode).
2
clock undivided mode), and set the CM06 bit to 0 (CM16 and CM17 bits enable).
2
this bit cannot be modified.
b6
0
b5
0
0
7
b5
0 1
b4
b4
b3
b3
page 53
b2
b2
b1
b1
b0
f o
b0
Bit Symbol
(b7-b4)
4
CCLK0
CCLK1
CCLK2
CCLK3
5
PLC00
PLC01
PLC02
PLC07
Symbol
(b6-b5)
Symbol
CCLKR
8
(b4)
(b3)
Bit
Symbol
PLC0
(1)
(1,2)
PLL multiplying factor
select bit
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined
Operation enable bit
Reserved bit
Reserved bit
CAN0 CPU interface
sleep bit
Nothing is assigned. If necessary, set to 0. When read,
the content is 0
CAN0 clock select bits
Bit Name
Bit Name
(3)
Address
025F
Address
001C
16
(3)
16
(4)
(2)
b2
Set to 1
Set to 0
0: PLL Off
1: PLL On
0 0 0:
0 0 1: Multiply by 2
0 1 0: Multiply by 4
0 1 1:
1 0 0:
1 0 1:
1 1 0:
1 1 1:
After Reset
00
b1b0
0: CAN0 CPU interface operating
1: CAN0 CPU interface in sleep
0 0 0 No division
0 0 1: Divide-by-2
0 1 0: Divide-by-4
0 1 1: Divide-by-8
1 0 0: Divide-by-16
1 0 1:
1 1 0:
1 1 1:
b2 b1 b0
16
Do not set
Do not set
After Reset
0001X010
Inhibited
Function
Function
2
2
(main
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW