M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 211

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
1
. v
J
Figure 14.12 Transfer format
Figure 14.11 Polarity of transfer clock
6
0
1
C
9
1 .
B
2 /
0
2
14.1.1.3 LSB First/MSB First Select Function
9
1
M
Use the UFORM bit in the UiC0 register (i=0 to 2) to select the transfer format. Figure 14.12 shows
the transfer format.
0
G
14.1.1.2 CLK Polarity Select Function
1
r a
0 -
o r
Use the CKPOL bit in the UiC0 register (i=0 to 2) to select the transfer clock polarity. Figure 14.11
shows the polarity of the transfer clock.
3 .
1
u
, 0
1
p
2
2
0
R
R
(1) When the CKPOL bit in the UiC0 register is set to 0 (transmit data output at the falling edge
CLK
T
CLK
T
(2) When the CKPOL bit in the UiC0 register is set to 1 (transmit data output at the rising
i = 0 to 2
NOTES:
(1) When the UFORM bit in the UiC0 register 0 (LSB first)
(2) When the UFORM bit in the UiC0 register is set to 1 (MSB first)
0
X
X
X
X
CLK
T
R
CLK
T
R
i = 0 to 2
NOTE:
D
D
D
D
7
and the receive data taken in at the rising edge of the transfer clock)
edge and the receive data taken in at the falling edge of the transfer clock)
X
X
X
X
i
i
i
i
i
i
D
D
1. This applies to the case where the CKPOL bit in the UiC0 register is set to 0 (transmit data output at
D
D
1. This applies to the case where the UFORM bit in the UiC0 register is set to 0 (LSB first) and the
2. When not transferring, the CLKi pin outputs a high signal.
i
i
i
i
i
i
the falling edge and the receive data taken in at the rising edge of the transfer clock) and the
UiLCH bit in the UiC1 register 0 (no reverse).
UiLCH bit in the UiC1 register is set to 0 (no reverse).
page 185
D0
D
D
D
0
0
0
f o
D0
D
D
D
0
7
7
4
5
D
D
D
D
8
1
1
1
1
D
D
D
D
1
1
6
6
D
D
D
D
2
2
2
2
D
D
D
D
2
5
2
5
D
D
D
D
3
3
3
3
D
D
D
D
3
4
3
4
D
D
D
D
4
4
4
4
D
D
D
D
4
3
4
3
D
D
D
D
5
5
5
5
D
D
D
D
5
2
5
2
D
D
D
D
6
6
6
6
D
D
D
D
6
6
1
1
D
D
D
D
7
7
7
7
D
D
D
D
7
0
7
0
(2)
(3)
14. Serial I/O