M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 218

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
1
. v
J
Figure 14.17 Receive Operation
Table 14.9 Example of Bit Rates and Settings
6
0
C
1
9
Bit Rate
1 .
B
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
2 /
(bps)
14400
19200
28800
31250
38400
51200
UiC1 register
RE bit
Transfer clock
UiBRG count
source
RxDi
RTSi
SiRIC register
IR bit
UiC1 register
RI bit
The above timing diagram applies to the case where the register bits are set as follows:
0
14.1.2.1 Bit Rates
2
i = 0 to 2
1200
2400
4800
9600
9
1
• Set the PRYE bit in the UiMR register to 0 (parity disabled)
• Set the STPS bit in the UiMR register to 0 (1 stop bit)
• Set the CRD bit in the UiC0 register to 0 (CTSi/RTSi enabled), the CRS bit to 1 (RTSi selected)
M
In UART mode, the frequency set by the UiBRG register (i=0 to 2) divided by 16 become the bit rates.
Table 14.9 lists example of bit rate and settings.
0
G
1
r a
0 -
o r
3 .
1
u
, 0
1
p
Count Source
2
2
0
of BRG
0
7
“L”
1
0
1
0
“H”
1
0
f8
f8
f8
f1
f1
f1
f1
f1
f1
f1
page 192
Reception triggered when transfer clock
is generated by falling edge of start bit
Peripheral Function Clock : 16MHz
Set Value of BRG : n Actual Time (bps) Set Value of BRG : n Actual Time (bps)
f o
4
Start
103(67h)
103(67h)
bit
31(1Fh)
5
51(33h)
25(19h)
68(44h)
51(33h)
34(22h)
25(19h)
19(13h)
8
Sampled “L”
Cleared to 0 when interrupt request is accepted, or cleared to 0 by program
D
0
14493
19231
28571
31250
38462
50000
Receive data taken in
1202
9615
2404
4808
Transferred from UARTi receive
register to UiRB register
D
1
Peripheral Function Clock : 20MHz
D
129(81h)
129(81h)
7
42(2Ah)
64(40h)
32(20h)
86(56h)
64(40h)
39(27h)
32(20h)
24(18h)
Stop bit
Read out from
UiRB register
14368
19231
29070
31250
37879
50000
1202
2404
4735
9615