M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 15

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17. CAN Module ______________________________________________ 287
16.6 I
16.7 I
16.8 I
16.9 START Condition Generation Method ....................................................................... 278
16.10 START Condition Duplicate Protect Function ........................................................... 279
16.11 STOP Condition Generation Method ........................................................................ 279
16.12 START/STOP Condition Detect Operation ............................................................... 281
16.13 Address Data Communication ................................................................................. 282
16.14 Precautions ............................................................................................................... 284
17.1 CAN Module-Related Registers ................................................................................. 288
16.5.3 Bit 2: Slave Address Comparison Flag (AAS) ..................................................... 269
16.5.4 Bit 3: Arbitration Lost Detection Flag (AL) ........................................................... 269
16.5.5 Bit 4: I
16.5.6 Bit 5: Bus Busy Flag (BB) .................................................................................... 270
16.5.7 Bit 6: Communication Mode Select Bit (Transfer Direction Select Bit: TRX) ....... 271
16.5.8 Bit 7: Communication mode select bit (master/slave select bit: MST) ................ 271
16.6.1 Bit 0 : Interrupt Enable Bit by STOP Condition (SIM ) ......................................... 272
16.6.2 Bit 1: Interrupt Enable Bit at the Completion of Data Receive (WIT) .................. 272
16.6.3 Bits 2,3 : Port Function Select Bits PED, PEC .................................................... 273
16.6.4 Bits 4,5 : SDA/SCL Logic Output Value Monitor Bits SDAM/SCLM .................... 274
16.6.5 Bits 6,7 : I
16.6.6 Address Receive in STOP/WAIT Mode ............................................................... 274
16.7.1 Bit0: Time-Out Detection Function Enable Bit (TOE) .......................................... 276
16.7.2 Bit1: Time-Out Detection Flag (TOF ).................................................................. 276
16.7.3 Bit2: Time-Out Detection Period Select Bit (TOSEL) .......................................... 276
16.7.4 Bits 3,4,5: I
16.7.5 Bit7: STOP Condition Detection Interrupt Request Bit (SCPIN).......................... 276
16.8.1 Bit0-Bit4: START/STOP Condition Setting Bits (SSC0-SSC4) ............................ 277
16.8.2 Bit5: SCL/SDA Interrupt Pin Polarity Select Bit (SIP) .......................................... 277
16.8.3 Bit6 : SCL/SDA Interrupt Pin Select Bit (SIS) ...................................................... 277
16.8.4 Bit7: START/STOP Condition Generation Select Bit (STSPSEL) ....................... 277
16.13.1 Example of Master Transmit ............................................................................. 282
16.13.2 Example of Slave Receive ................................................................................ 283
17.1.1 CAN0 Message Box ............................................................................................. 289
17.1.2 Acceptance Mask Registers ................................................................................. 291
17.1.3 CAN SFR Registers ............................................................................................. 292
2
2
2
C0 Control Register 1 (S3D0 register) .................................................................... 272
C0 Control Register 2 (S4D0 Register) ................................................................... 275
C0 START/STOP Condition Control Register (S2D0 Register) ............................... 277
2
C bus Interface Interrupt Request Bit (PIN) ............................................. 270
2
C System Clock Select Bits ICK0, ICK1 ............................................ 274
2
C System Clock Select Bits (ICK2-4) ............................................... 276
A-6