M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 148

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
1
. v
J
Figure 12.22 Operation timing when measuring a pulse width
6
Figure 12.21 Operation timing when measuring a pulse period
0
C
1
9
1 .
B
2 /
NOTES:
0
i = 0 to 2
The MR3 bit in the
TBiMR register
2
Timing at which counter
reaches 0000
TBiS bit
TBiMR register's
MR3 bit
TBiS bit
TBiIC register's
IR bit
Measurement pulse
TBiIC register's
IR bit
Reload register
transfer timing
NOTES:
Count source
Measurement pulse
Timing at which counter
reaches 0000
i = 0 to 2
9
Reload register
transfer timing
1
M
0
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where bits MR1 and MR0 in the TBiMR register are 00
G
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where bits MR1 to MR0 in the TBiMR register are 10
1
r a
o r
0 -
interval from falling edge to falling edge of the measurement pulse).
from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the
measurement pulse).
3 .
1
u
, 0
Count source
1
p
2
2
0
16
16
0
Bits TB0S to TB2S are assigned to the bit 5 to bit 7 in the TABSR register.
7
Bits TB0S to TB2S are assigned to the bit 5 to bit 7 in the TABSR register.
counter
counter
page 122
“H”
“L”
“H”
“L”
1
0
1
0
1
0
1
0
1
0
1
0
f o
4
5
8
Set to 0 upon accepting an interrupt request or by program
Set to 0 upon accepting an interrupt request or by
program
Transfer
(undefined
value)
(1)
Transfer
(measured value)
(1)
Transfer
(undefined value)
(1)
Transfer
(measured
value)
(1)
Transfer
(measured value)
(1)
Transfer
(measured value)
(1)
2
(measure the interval
2
(measure the
(1)
(2)