MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 449

• Manufacturer Part Number: MC68HC08AZ60ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

25.6 Control Timing
MC68HC08AZ60A — Rev 0.0
MOTOROLA
Bus Operating Frequency (4.5–5.5 V — V
Internal Clock Period (1/f
RESET Pulse Width Low
IRQ Interrupt Pulse Width Low (Edge-Triggered)
IRQ Interrupt Pulse Period
16-Bit Timer
MSCAN Wake-up Filter Pulse Width (see Note 4)
Input Capture Pulse Width (see Note 2)
Input Capture Period
Input Clock Pulse Width
POR Rise Time Ramp Rate (see Note 7)
High COP Disable Voltage (see Note 8)
Monitor Mode Entry Voltage on IRQ
2.Run (Operating) I
No dc loads. Less than 100 pF on all outputs. C
tance linearly affects run I
3.Wait I
loads. Less than 100 pF on all outputs, C
linearly affects wait I
4.Stop I
5.Maximum is highest voltage that POR is guaranteed.
6.Maximum is highest voltage that POR is possible.
7.If minimum V
minimum V
8.See
9.Although I
10.See monitor mode description within
11.When subjected to a Human Body Model (HBM) ESD event as specified in AEC Q100-002 these pins may exhibit recov-
erable leakage values within the specification indicated.
(see Note 10)
1.V
DD
Computer Operating Properly (COP)
= 5.0 Vdc
DD
DD
measured using external square wave clock source (f
measured with OSC1 = V
DD
DD
Characteristic
is reached.
DD
is proportional to bus frequency, a current of several mA is present even at very low frequencies.
BUS
is not reached before the internal POR reset is released, RST must be driven low externally until
0.5v, V
DD
DD
measured using external square wave clock source (f
)
. Measured with all modules enabled.
SS
DD
. Measured with all modules enabled.
= 0 Vdc, T
SS
A
.
DD
Computer Operating Properly (COP)
= –40 C to T
L
Electrical Specifications
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance
Only)
on page 189. V
L
Table 25-5
= 20 pF on OSC2. All ports configured as inputs. OSC2 capaci-
Table 25-4
A (MAX)
, unless otherwise noted.
HI
t
Symbol
TCH,
applied to RST.
BUS
t
TH,
t
t
f
t
t
WUP
t
TLTL
BUS
t
R
ILHI
ILIL
cyc
RL
V
V
= 8.4 MHz). All inputs 0.2 Vdc from rail. No dc
POR
t
t
HI
HI
TL
TCL
BUS
(1/f
on page 189. V
= 8.4 MHz). All inputs 0.2 V from rail.
Note 3
Note 3
Min
OP
119
1.5
1.5
—
2
2
TBD
TBD
0.02
) + 5
HI
applied to IRQ or RST.
Electrical Specifications
Max
8.4
—
—
—
—
—
—
—
5
Advance Information
TBD
TBD
—
Control Timing
MHz
Unit
t
t
t
t
t
ns
ns
cyc
cyc
cyc
cyc
cyc
V/ms
s
V
V
449