MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 203

• Manufacturer Part Number: MC68HC08AZ60ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC08AZ60A — Rev 0.0
MOTOROLA
IRQ Status/Control Register (ISCR)
Register Name
NOTE:
When an interrupt pin is edge-triggered only, the interrupt latch remains
set until a vector fetch, software clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the
interrupt latch remains set until both of the following occur:
The vector fetch or software clear may occur before or after the interrupt
pin returns to ‘1’. As long as the pin is low, the interrupt request remains
pending. A reset will clear the latch and the MODE control bit, thereby
clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the ISCR masks all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the corresponding IMASK bit is clear.
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests. See
2.
Read:
Write:
•
•
Table 15-1. IRQ I/O Register Summary
Vector fetch or software clear
Return of the interrupt pin to ‘1’
Bit 7
R
R
0
External Interrupt Module (IRQ)
= Reserved
6
R
0
5
R
0
R
4
0
IRQF
3
R
ACK
External Interrupt Module (IRQ)
2
0
IMASK
Functional Description
1
Advance Information
MODE $001A
Bit 0
Figure 15-
Addr.
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