MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 335

• Manufacturer Part Number: MC68HC08AZ60ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

20.8.2 Data Direction Register F (DDRF)
MC68HC08AZ60A — Rev 0.0
MOTOROLA
NOTE:
NOTE:
$000D
DDRF
TBCH[1:0] — Timer B Channel I/O Bits
Data direction register F(DDRF) does not affect the data direction of port
F pins that are being used by TIMA and TIMB. However, the DDRF bits
always determine whether reading port F returns the states of the
latches or the states of the pins. See
Data direction register F determines whether each port F pin is an input
or an output. Writing a logic one to a DDRF bit enables the output buffer
for the corresponding port F pin; a logic zero disables the output buffer.
DDRF[6:0] — Data Direction Register F Bits
Avoid glitches on port F pins by writing to the port F data register before
changing data direction register F bits from 0 to 1.
Reset:
Read:
Write:
The PTF5/TBCH1-PTF4/TBCH0 pins are the TIMB input
capture/output compare pins. The edge/level select bits,
ELSxB:ELSxA, determine whether the PTF5/TBCH1-PTF4/TBCH0
pins are timer channel I/O pins or general purpose I/O pins. See
Status and Control Register
These read/write bits control port F data direction. Reset clears
DDRF[6:0], configuring all port F pins as inputs.
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
Figure 20-17. Data Direction Register F (DDRF)
Bit 7
0
= Unimplemented
DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0
6
0
I/O Ports
5
0
on page 295.
4
0
Table
3
0
20-7.
2
0
Advance Information
1
0
I/O Ports
TIMB
Bit 0
Port F
0
335