MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 197

• Manufacturer Part Number: MC68HC08AZ60ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

14.4.1 Polled LVI Operation
14.4.2 Forced Reset Operation
MC68HC08AZ60A — Rev 0.0
MOTOROLA
LVI Status Register (LVISR) LVIOUT
DETECTOR
LOW V
Register Name
V
DD
DD
V
V
DD
DD
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
In applications that can operate at V
software can monitor V
register, the LVIPWR bit must be at logic ‘1’ to enable the LVI module
and the LVIRST bit must be at logic ‘0’ to disable LVI resets.
In applications that require V
enabling LVI resets allows the LVI module to reset the MCU when V
falls to the LVI
consecutive CPU cycles. In the mask option register, the LVIPWR and
> LVI
< LVI
Figure 14-1. LVI Module Block Diagram
TRIP
CPU CLOCK
TRIP
= 0
= 1
ANLGTRIP
Table 14-1. LVI I/O Register Summary
FROM MORA
LVIPWR
Bit 7
DIGITAL FILTER
Low Voltage Inhibit (LVI)
TRIPF
Filter Bypass
FROM MORA
Stop Mode
LVISTOP
V
= Unimplemented
DD
level and remains at or below that level for 9 or more
6
DD
by polling the LVIOUT bit. In the mask option
LVIOUT
5
DD
to remain above the LVI
4
FROM MORA
DD
LVIRST
levels below the LVI
3
2
Low Voltage Inhibit (LVI)
Functional Description
1
Advance Information
LVI RESET
TRIPF
TRIPF
Bit 0
level,
level,
$FE0F
Addr.
DD
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