MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 418

• Manufacturer Part Number: MC68HC08AZ60ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Timer Interface Module A (TIMA)
23.7 TIMA During Break Interrupts
23.8 I/O Signals
23.8.1 TIMA Clock Pin (PTD6/ATD14/TACLK)
Advance Information
418
A break interrupt stops the TIMA counter and inhibits input captures.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state (see
(SBFCR)
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
Port D shares one of its pins with the TIMA. Port E shares two of its pins
with the TIMA and port F shares four of its pins with the TIMA.
PTD6/ATD14/TACLK is an external clock input to the TIMA prescaler.
The six TIMA channel I/O pins are PTE2/TACH0, PTE3/TACH1,
PTF0/TACH2, PTF1/TACH3, PTF2, and PTF3.
PTD6/ATD14/TACLK is an external clock input that can be the clock
source for the TIMA counter instead of the prescaled internal bus clock.
Select the PTD6/ATD14/TACLK input by writing logic 1s to the three
on page 137).
Timer Interface Module A (TIMA)
SIM Break Flag Control Register
MC68HC08AZ60A — Rev 0.0
MOTOROLA