MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 259

• Manufacturer Part Number: MC68HC08AZ60ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

17.6.4 Transmission Initiation Latency
MC68HC08AZ60A — Rev 0.0
MOTOROLA
(FOR REFERENCE)
CAPTURE STROBE
(FROM MASTER)
(FROM SLAVE)
SCK (CPOL =’0’)
SS (TO SLAVE)
SCK (CPOL =1)
SCK CYCLE #
MOSI
MISO
When the SPI is configured as a master (SPMSTR = ‘1’), transmissions
are started by a software write to the SPDR. CPHA has no effect on the
delay to the start of the transmission, but it does affect the initial state of
the SCK signal. When CPHA = ‘0’, the SCK signal remains inactive for
the first half of the first SCK cycle. When CPHA = ‘1’, the first SCK cycle
begins with an edge on the SCK line from its inactive to its active level.
The SPI clock rate (selected by SPR1:SPR0) affects the delay from the
write to SPDR and the start of the SPI transmission. See
The internal SPI clock in the master is a free-running derivative of the
internal MCU clock. It is only enabled when both the SPE and SPMSTR
bits are set to conserve power. SCK edges occur halfway through the
low time of the internal MCU clock. Since the SPI clock is free-running,
it is uncertain where the write to the SPDR will occur relative to the
slower SCK. This uncertainty causes the variation in the initiation delay
shown in
time. That is, the maximum delay is two MCU bus cycles for DIV2, eight
MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU
bus cycles for DIV128.
MSB
MSB
1
Figure
BIT 6
BIT 6
Serial Peripheral Interface (SPI)
2
17-6. This delay will be no longer than a single SPI bit
BIT 5
BIT 5
3
BIT 4
BIT 4
4
BIT 3
BIT 3
5
BIT 2
BIT 2
6
Serial Peripheral Interface (SPI)
BIT 1
BIT 1
7
Transmission Formats
Advance Information
LSB
8
Figure
LSB
17-6.
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