MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 442

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MC68HC08AZ60ACFU

Manufacturer Part Number
MC68HC08AZ60ACFU
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
Analog-to-Digital Converter (ADC-15)
24.8.2 ADC Data Register
24.8.3 ADC Input Clock Register
Advance Information
442
Address:
Address:
One 8-bit result register is provided. This register is updated each time
an ADC conversion completes.
This register selects the clock frequency for the ADC.
ADIV2–ADIV0 — ADC Clock Prescaler Bits
Reset:
Reset:
Read:
Write:
Read:
Write:
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide
ratio used by the ADC to generate the internal ADC clock.
2
set to approximately 1 MHz.
shows the available clock configurations. The ADC clock should be
$003A
ADIV2
$0039
Analog-to-Digital Converter (ADC-15)
Bit 7
Bit 7
AD7
Figure 24-4. ADC Input Clock Register (ADICLK)
R
R
R
0
Figure 24-3. ADC Data Register (ADR)
= Reserved
= Reserved
ADIV1
AD6
R
6
6
0
ADIV0
AD5
R
5
5
0
Indeterminate after Reset
ADICLK
AD4
R
4
4
0
AD3
R
R
3
3
0
0
MC68HC08AZ60A — Rev 0.0
AD2
R
R
2
2
0
0
AD1
R
R
1
1
0
0
MOTOROLA
Table 24-
Bit 0
Bit 0
AD0
R
R
0
0

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