MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 318
MC68HC08AZ60ACFU
Manufacturer Part Number
MC68HC08AZ60ACFU
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC08AZ60ACFU.pdf
(480 pages)
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I/O Ports
20.3.2 Data Direction Register A (DDRA)
Advance Information
318
NOTE:
DDRA
$0004
Reset:
Read:
Write:
Data direction register A determines whether each port A pin is an input
or an output. Writing a logic one to a DDRA bit enables the output buffer
for the corresponding port A pin; a logic zero disables the output buffer.
DDRA[7:0] — Data direction register A Bits
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 20-3
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
DDRA7
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
Figure 20-2 Data Direction Register A (DDRA)
Bit 7
READ DDRA ($0004)
WRITE DDRA ($0004)
WRITE PTA ($0000)
READ PTA ($0000)
0
shows the port A I/O logic.
DDRA6
6
0
RESET
Figure 20-3. Port A I/O Circuit
I/O Ports
DDRA5
5
0
DDRA4
DDRAx
4
0
PTAx
DDRA3
3
0
MC68HC08AZ60A — Rev 0.0
DDRA2
2
0
DDRA1
1
0
MOTOROLA
DDRA0
Bit 0
PTAx
0
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