MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 198

• Manufacturer Part Number: MC68HC08AZ60ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Low Voltage Inhibit (LVI)
14.4.3 False Reset Protection
14.5 LVI Status Register (LVISR)
Advance Information
198
$FE0F
LVISR
Reset:
Read:
Write:
LVIRST bits must be at ‘1’ to enable the LVI module and to enable LVI
resets.
The V
supply noise. In order for the LVI module to reset the MCU,V
remain at or below the LVI
cycles. V
MCU out of reset.
The LVI status register flags V
LVIOUT — LVI Output Bit
This read-only flag becomes set when V
voltage for 32-40 CGMXCLK cycles. (See
the LVIOUT bit.
LVIOUT
DD
Bit 7
0
Figure 14-2. LVI Status Register (LVISR)
pin level is digitally filtered to reduce false resets due to power
DD
must be above LVI
= Unimplemented
Low Voltage Inhibit (LVI)
6
0
0
0
5
0
TRIPF
DD
TRIPR
level for 9 or more consecutive CPU
0
4
0
voltages below the LVI
for only one CPU cycle to bring the
0
3
0
DD
Table
falls below the LVI
MC68HC08AZ60A — Rev 0.0
0
2
0
14-2). Reset clears
TRIPF
1
0
0
level
MOTOROLA
DD
must
TRIPF
.
Bit 0
0
0