MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 330

• Manufacturer Part Number: MC68HC08AZ60ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

I/O Ports
Advance Information
330
NOTE:
NOTE:
MISO — Master In/Slave Out
SS — Slave Select
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SPI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. See
TACH[1:0] — Timer A Channel I/O Bits
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the TIMA. However, the DDRE bits
always determine whether reading port E returns the states of the
latches or the states of the pins. See
The PTE5/MISO pin is the master in/slave out terminal of the SPI
module. When the SPI enable bit, SPE, is clear, the SPI module is
disabled, and the PTE5/MISO pin is available for general-purpose
I/O. See
The PTE4/SS pin is the slave select input of the SPI module. When
the SPE bit is clear, or when the SPI master bit, SPMSTR, is set and
MODFEN bit is low, the PTE4/SS pin is available for general-purpose
I/O. See
a slave, the DDRF0 bit in data direction register E (DDRE) has no
effect on the PTE4/SS pin.
The PTE3/TACH1–PTE2/TACH0 pins are the TIMA input
capture/output compare pins. The edge/level select bits,
ELSxB:ELSxA, determine whether the PTE3/TACH1–PTE2/TACH0
pins are timer channel I/O pins or general-purpose I/O pins. See
Channel Status and Control Registers
SPI Control Register
SPI Control Register
I/O Ports
(SPCR). When the SPI is enabled as
(SPCR).
Table
Table
20-6.
20-6.
on page 424.
MC68HC08AZ60A — Rev 0.0
MOTOROLA
TIMA