MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 324

• Manufacturer Part Number: MC68HC08AZ60ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

I/O Ports
20.5.2 Data Direction Register C (DDRC)
Advance Information
324
NOTE:
DDRC
$0006
Reset:
Read:
Write:
Data direction register C determines whether each port C pin is an input
or an output. Writing a logic one to a DDRC bit enables the output buffer
for the corresponding port C pin; a logic zero disables the output buffer.
MCLKEN — MCLK Enable Bit
DDRC[5:0] — Data Direction Register C Bits
Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
This read/write bit enables MCLK to be an output signal on PTC2. If
MCLK is enabled, DDRC2 has no effect. Reset clears this bit.
These read/write bits control port C data direction. Reset clears
DDRC[7:0], configuring all port C pins as inputs.
MCLKEN
Figure 20-8. Data Direction Register C (DDRC)
1 = MCLK output enabled
0 = MCLK output disabled
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
Bit 7
0
= Unimplemented
6
0
0
I/O Ports
DDRC5
5
0
DDRC4
4
0
DDRC3
3
0
MC68HC08AZ60A — Rev 0.0
DDRC2
2
0
DDRC1
1
0
MOTOROLA
DDRC0
Bit 0
0