MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 269

• Manufacturer Part Number: MC68HC08AZ60ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

17.10 Low-Power Modes
17.10.1 WAIT Mode
17.10.2 STOP Mode
17.11 SPI During Break Interrupts
MC68HC08AZ60A — Rev 0.0
MOTOROLA
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
The SPI module remains active after the execution of a WAIT instruction.
In WAIT mode the SPI module registers are not accessible by the CPU.
Any enabled CPU interrupt request from the SPI module can bring the
MCU out of WAIT mode.
If SPI module functions are not required during WAIT mode, power
consumption can be reduced by disabling the SPI module before
executing the WAIT instruction.
To exit WAIT mode when an overflow condition occurs, the OVRF bit
should be enabled to generate CPU interrupt requests by setting the
error interrupt enable bit (ERRIE). See Interrupts.
The SPI module is inactive after the execution of a STOP instruction.
The STOP instruction does not affect register conditions. SPI operation
resumes after an external interrupt. If STOP mode is exited by reset, any
transfer in progress is aborted, and the SPI is reset.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. See SIM Break Flag Control
Register (SBFCR).
To allow software to clear status bits during a break interrupt, a ‘1’ should
be written to the BCFE bit. If a status bit is cleared during the break state,
it remains cleared when the MCU exits the break state.
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
Advance Information
Low-Power Modes
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