h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 989

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

22A.1 Overview
The chip has a built-in clock pulse generator (CPG) that generates the system clock ( ), the bus
master clock, and internal clocks.
The clock pulse generator consists of an oscillator, PLL (phase-locked loop) circuit, clock
selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock
oscillator, and waveform shaping circuit. The frequency can be changed by means of the PLL
circuit in the CPG. Frequency changes are performed by software by means of settings in the
system clock control register (SCKCR) and low-power control register (LPWRCR).
22A.1.1 Block Diagram
Figure 22A-1 shows a block diagram of the clock pulse generator.
(H8S/2636 Group, H8S/2638 Group, H8S/2630 Group)
Section 22A Clock Pulse Generator (H8S/2636 Group, H8S/2638 Group, H8S/2630 Group)
EXTAL
XTAL
OSC1
OSC2
Legend:
LPWRCR:
SCKCR:
Note:
*
*
*
Low-power control register
System clock control register
Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and
W-mask versions only.
These functions cannot be used with the other versions.
See section 22A.7, Subclock Oscillator, for the method of fixing pins OSC1 and OSC2.
oscillator
Subclock
oscillator
System
clock
Figure 22A-1 Block Diagram of Clock Pulse Generator
Section 22A Clock Pulse Generator
(×1, ×2, ×4)
Generation
PLL circuit
Waveform
LPWRCR
Circuit
WDT1 count clock
STC1, STC0
φSUB
selection
circuit
Clock
System clock
to φ pin
Rev. 6.00 Feb 22, 2005 page 929 of 1484
clock divider
Medium-
speed
supporting modules
Internal clock to
φ/2 to
φ/32
φ
selection
SCKCR
master
circuit
clock
Bus
Bus master clock
REJ09B0103-0600
to CPU and DTC
SCK2 to SCK0