h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 647

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

15.3.9
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 15-20 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
15.3.10 Initialization of Internal State
The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed by (1) setting bits CLR3 to CLR0 in the DDCSWR register or (2)
clearing the ICE bit. For details of settings for bits CLR3 to CLR0, see section 15.2.8, DDC
Switch Register (DDCSWR).
Scope of Initialization: The initialization executed by this function covers the following items:
TDRE and RDRF internal flags
Transmit/receive sequencer and internal operating clock counter
Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data
output, etc.)
SCL or
SDA input
signal
Sampling
clock
Section 15 I
Noise Canceler
D
Sampling clock
System clock
2
period
C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630)
Figure 15-20 Block Diagram of Noise Canceler
Latch
C
Q
D
Latch
C
Rev. 6.00 Feb 22, 2005 page 587 of 1484
Q
detector
Match
REJ09B0103-0600
Internal
SCL or
SDA
signal