h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 833

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

FLER bit setting conditions are as follows:
1. When the flash memory of the relevant address area is read during programming/erasing
2. Immediately after exception handling (excluding a reset) during programming/erasing
3. When a SLEEP instruction (including software standby) is executed during
4. When the CPU releases the bus to the DTC
Error protection is released only by a reset and in hardware standby mode.
Figure 21A-14 shows the flash memory state transition diagram.
Legend:
RD: Memory read possible
VF: Verify-read possible
PR: Programming possible
ER: Erasing possible
RD VF PR ER FLER = 0
(including vector read and instruction fetch)
programming/erasing
Program mode
occurrence
RD VF PR ER FLER = 1
Erase mode
Error protection mode
Error
Figure 21A-14 Flash Memory State Transitions
Error occurrence
(software standby)
RD: Memory read not possible
VF: Verify-read not possible
PR: Programming not possible
ER: Erasing not possible
RES = 0 or HSTBY = 0
Software
standby mode
Software standby
mode release
RES = 0 or
HSTBY = 0
Rev. 6.00 Feb 22, 2005 page 773 of 1484
HSTBY = 0
RES = 0 or
RD VF PR ER FLER = 1
Error protection mode
FLMCR1, FLMCR2, (except bit FLER)
EBR1, EBR2 initialization state
Section 21A ROM (H8S/2636 Group)
(software standby)
RD VF PR ER FLER = 0
(hardware protection)
Reset or standby
FLMCR1, FLMCR2,
EBR1, EBR2
initialization state
REJ09B0103-0600