h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 1425

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

TIOR3L—Timer I/O Control Register 3L
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the
Bit
Initial value
Read/Write
Notes: 1.
TGR3D I/O Control
register operates as a buffer register.
0
1
0
1
0
1
2.
0
1
0
1
0
1
*
When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and φ/1 is used as the
TCNT4 count clock, this setting is invalid and input capture is not generated.
When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register,
this setting is invalid and input capture/output compare is not generated.
0
1
0
1
0
1
0
1
0
1
*
*
IOD3
R/W
TGR3D is
output
compare
register *
TGR3D is
input
capture
register *
7
0
2
2
Note: 1. When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register,
TGR3C I/O Control
0
1
IOD2
R/W
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCD3 pin
Capture input
source is channel
4/count clock
6
0
0
1
0
1
0
1
0
1
0
1
*
this setting is invalid and input capture/output compare is not generated.
0
1
0
1
0
1
0
1
0
1
*
*
IOD1
R/W
TGR3C is
output
compare
register *
TGR3C is
input
capture
register *
5
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT4 count-up/
count-down *
1
1
IOD0
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCC3 pin
Capture input
source is channel
4/count clock
R/W
4
0
1
Rev. 6.00 Feb 22, 2005 page 1365 of 1484
H'FE83
IOC3
R/W
3
0
*: Don't care
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT4 count-up/
count-down
Appendix B Internal I/O Register
IOC2
R/W
2
0
IOC1
R/W
1
0
REJ09B0103-0600
*: Don't care
IOC0
R/W
0
0
TPU3