h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 1041

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Bit 3—Output Port Enable (OPE): This bit specifies whether the output of the address bus and
bus control signals (
software standby mode, watch mode, and when making a direct transition.
Bits 2 to 0—Reserved: These bits always return 0 when read, and cannot be written to.
23B.2.2 System Clock Control Register (SCKCR)
SCKCR is an 8-bit readable/writable register that performs clock output control and medium-
speed mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7— Clock Output Disable (PSTOP): In combination with the DDR of the applicable port,
this bit controls output. See section 23B.12, Clock Output Disable Function for details.
Bit 7
PSTOP
0
1
HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF,
Bit 3
OPE
0
1
High-Speed Mode,
Medium-Speed Mode,
Subactive Mode
Fixed high
Description
In software standby mode, watch mode, and when making a direct transition, address
bus and bus control signals are high-impedance.
In software standby mode, watch mode, and when making a direct transition, the
output state of the address bus and bus control signals is retained.
output (initial value)
Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF,
HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF]
A S
,
R D
,
H W R
¾
¾
,
Sleep Mode,
Subsleep Mode
Fixed high
L W R
output
¾
¾
) is retained or set to high-impedance state in the
Description
¾
¾
Rev. 6.00 Feb 22, 2005 page 981 of 1484
Software Standby
Mode, Watch Mode,
Direct Transition
Fixed high
Fixed high
Hardware Standby
Mode
High impedance
High impedance
REJ09B0103-0600
(Initial value)