h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 657

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

SDA
SCL
TRS
Notes on ICDR Reads and ICCR Access in Slave Transmit Mode
In a transmit operation in the slave mode of the I
register or read or write to the ICCR register during the period indicated by the shaded portion
in figure 15-25.
Normally, when interrupt processing is triggered in synchronization with the rising edge of the
9th clock cycle, the period in question has already elapsed when the transition to interrupt
processing takes place, so there is no problem with reading the ICDR register or reading or
writing to the ICCR register.
To ensure that the interrupt processing is performed properly, one of the following two
conditions should be applied.
(1) Make sure that reading received data from the ICDR register, or reading or writing to the
(2) Monitor the BC2 to BC0 counter in the ICMR register and, when the value of BC2 to BC0
ICCR register, is completed before the next slave address receive operation starts.
is 000 (8th or 9th clock cycle), allow a waiting time of at least 2 transfer clock cycles in
order to involve the problem period in question before reading from the ICDR register, or
reading or writing to the ICCR register.
Figure 15-25 ICDR Read and ICCR Access Timing in Slave Transmit Mode
Section 15 I
Address received
R/W
8
2
C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630)
Detection of 9th clock
cycle rising edge
A
9
Period when ICDR reads and ICCR
reads and writes are prohibited
(6 system clock cycles)
Waveforms if
problem occurs
2
C bus interface, do not read the ICDR
Rev. 6.00 Feb 22, 2005 page 597 of 1484
Data transmission
REJ09B0103-0600
Bit 7
ICDR write