h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 1063

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

23B.13 Usage Notes
1. When making a transition to subactive mode or watch mode, set the DTC to enter module stop
2. The on-chip peripheral modules (DTC and TPU) which halt operation in subactive mode
3. A 1 is always returned when an attempt is made to read the pin status of I/O ports 1, 4, 9, or F
4. Operation cannot be guaranteed if a transition is made to the subactive mode, subsleep mode,
5. (H8S/2639 Group, H8S/2635 Group only) The subclock ( SUB) is frequency divided
HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF,
mode (write 1 to the relevant bits in MSTPCR), and then read the relevant bits to confirm that
they are set to 1 before mode transition. Do not clear module stop mode (write 0 to the relevant
bits in MSTPCR) until a transition from subactive mode to high-speed mode or medium-speed
mode has been performed.
If a DTC activation source occurs in subactive mode, the DTC will be activated only after
module stop mode has been cleared and high-speed mode or medium-speed mode has been
entered.
cannot clear an interrupt in subactive mode. Therefore, if a transition is made to subactive
mode while an interrupt is requested, the CPU interrupt source cannot be cleared. Disable the
interrupts of each on-chip peripheral module before executing a SLEEP instruction to enter
subactive mode or watch mode.
during operation in subactive mode. (In the case of port 1, pins 13 to 10 are readable.) In
addition, the ports may be used as output ports (except for ports 4 and 9). The procedure for
determining the pin status during operation in subactive mode is as follows.
[1] Use ports 3, A, B, C, D, E, H, and J as input ports.
[2] Use external interrupt inputs (IRQ0 to IRQ5). (If the level sense setting has been selected
or watch mode when the SUBSTP bit in LPWRCR is set to 1 (subclock generation prohibited).
To prevent problems, it should be confirmed that the SUBSTP bit has been cleared to 0 before
transitioning to the subactive mode, subsleep mode, or watch mode.
internally, so the clock oscillator does not halt even if a transition to the software standby
mode occurs when the SUBSTP bit in LPWRCR is cleared to 0. The SUBSTP bit in LPWRCR
should be set to 1 before transitioning to the software standby mode.
for the IRQ pins, an interrupt request is generated by a low-level input.)
Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF,
HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF]
Rev. 6.00 Feb 22, 2005 page 1003 of 1484
REJ09B0103-0600