h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 633

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Figure 15-10 Flowchart for Master Receive Mode (Receiving Multiple Bytes) (WAIT = 1)
Section 15 I
No
No
No
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
1 clock cycle wait state
2
Set ACKB = 0 (ICSR)
Set WAIT = 1 (ICMR)
Set ACKB = 1 (ICSR)
Set WAIT = 0 (ICMR)
Master receive mode
and SCP = 0 (ICCR)
Set TRS = 0 (ICCR)
Set TRS = 1 (ICCR)
C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630)
Write BBSY = 0
Final receive?
Read ICDR
Read ICDR
Read ICDR
Read ICDR
IRTR = 1?
IRTR = 1?
IRIC = 1?
IRIC = 1?
End
Yes
Yes
Yes
No
No
Yes
Yes
(Example)
[1] Set to receive mode
[2] Receive start, dummy read
[3] Receive wait state (IRIC set at falling edge of 8th clock cycle)
[4] Data receive completed judgment
[5] Read receive data
[6] Clear IRIC flag (cancel wait state)
[7] Set acknowledge data for final receive
[8] Wait time until TRS setting
[9] Set TRS to generate stop condition
[10] Read receive data
[11] Clear IRIC flag (cancel wait state)
[12] Receive wait state (IRIC set at falling edge of 8th clock cycle)
[13] Data receive completed judgment
[14] Clear IRIC flag (cancel wait state)
[15] Cancel wait mode
[16] Read final receive data
[17] Generate stop condition
or
Wait for end of reception of 1 byte (IRIC set at rising edge
of 9th clock cycle)
or
Wait for end of reception of 1 byte (IRIC set at rising edge
of 9th clock cycle)
Clear IRIC flag (IRIC flag should be cleared when WAIT = 0)
Rev. 6.00 Feb 22, 2005 page 573 of 1484
REJ09B0103-0600