h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 648

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 15 I
The following items are not initialized:
Notes on Initialization:
The value of the BBSY bit cannot be modified directly by this module clear function, but since the
stop condition pin waveform is generated according to the state and release timing of the SCL and
SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and
flags may also have an effect.
To prevent problems caused by these factors, the following procedure should be used when
initializing the IIC state.
1. Execute initialization of the internal state according to the setting of bits CLR3 to CLR0, or
2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBST bit
3. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0, or
4. Initialize (re-set) the IIC registers.
Rev. 6.00 Feb 22, 2005 page 588 of 1484
REJ09B0103-0600
Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, DDCSWR, and STCR)
Internal latches used to retain register read information for setting/clearing flags in the ICMR,
ICCR, ICSR, and DDCSWR registers
The value of the ICMR register bit counter (BC2 to BC0)
Generated interrupt sources (interrupt sources transferred to the interrupt controller)
Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be
taken as necessary.
Basically, other register flags are not cleared either, and so flag clearing measures must be
taken as necessary.
When initialization is performed by means of the DDCSWR register, the write data for bits
CLR3 to CLR0 is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written
to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as
BCLR. Similarly, when clearing is required again, all the bits must be written to
simultaneously in accordance with the setting.
If a flag clearing setting is made during transmission/reception, the IIC module will stop
transmitting/receiving at that point and the SCL and SDA pins will be released. When
transmission/reception is started again, register initialization, etc., must be carried out as
necessary to enable correct communication as a system.
according to the ICE bit.
to 0, and wait for two transfer rate clock cycles.
according to the ICE bit.
2
C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630)