h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 634

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 15 I
The procedure for receiving data sequentially, using the wait states (WAIT bit) for
synchronization with ICDR (ICDRR) read operations, is described below.
The procedure below describes the operation for receiving multiple bytes. Note that some of the
steps are omitted when receiving only 1 byte. Refer to figure 15-11 for details.
Rev. 6.00 Feb 22, 2005 page 574 of 1484
REJ09B0103-0600
Figure 15-11 Flowchart for Master Receive Mode (Receiving 1 Byte) (WAIT = 1)
2
C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630)
No
No
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Set ACKB = 0 (ICSR)
Set WAIT = 1 (ICMR)
Set ACKB = 1 (ICSR)
Set WAIT = 0 (ICMR)
Master receive mode
and SCP = 0 (ICCR)
Set TRS = 0 (ICCR)
Set TRS = 1 (ICCR)
Write BBSY = 0
Read ICDR
Read ICDR
IRIC = 1?
IRIC = 1?
End
Yes
Yes
(Example)
[1]
[2]
[3]
[7]
[9]
[11] Clear IRIC flag (cancel wait state)
[12] Wait for end of reception of 1 byte
[15] Cancel wait mode
[16] Read final receive data
[17] Generate stop condition
Set to receive mode
Receive start, dummy read
Set acknowledge data for final receive
Set TRS to generate stop condition
(IRIC set at rising edge of 9th clock cycle)
Clear IRIC flag (IRIC flag should be
cleared when WAIT = 0)
Receive wait state (IRIC set at falling edge
of 8th clock cycle) or
Wait for end of reception of 1 byte
(IRIC set at rising edge of 9th clock cycle)