h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 48

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

16.3 Operation .......................................................................................................................... 641
16.4 CAN Bus Interface ........................................................................................................... 666
16.5 Usage Notes ...................................................................................................................... 667
Section 17 A/D Converter
17.1 Overview........................................................................................................................... 671
17.2 Register Descriptions........................................................................................................ 675
Rev. 6.00 Feb 22, 2005 page xlviii of lx
16.2.4 Mailbox Configuration Register (MBCR) ........................................................... 614
16.2.5 Transmit Wait Register (TXPR) .......................................................................... 615
16.2.6 Transmit Wait Cancel Register (TXCR).............................................................. 616
16.2.7 Transmit Acknowledge Register (TXACK) ........................................................ 617
16.2.8 Abort Acknowledge Register (ABACK) ............................................................. 618
16.2.9 Receive Complete Register (RXPR).................................................................... 619
16.2.10 Remote Request Register (RFPR) ....................................................................... 620
16.2.11 Interrupt Register (IRR)....................................................................................... 621
16.2.12 Mailbox Interrupt Mask Register (MBIMR) ....................................................... 626
16.2.13 Interrupt Mask Register (IMR) ............................................................................ 627
16.2.14 Receive Error Counter (REC).............................................................................. 630
16.2.15 Transmit Error Counter (TEC) ............................................................................ 630
16.2.16 Unread Message Status Register (UMSR)........................................................... 631
16.2.17 Local Acceptance Filter Masks (LAFML, LAFMH)........................................... 632
16.2.18 Message Control (MC0 to MC15) ....................................................................... 634
16.2.19 Message Data (MD0 to MD15) ........................................................................... 638
16.2.20 Module Stop Control Register C (MSTPCRC) ................................................... 640
16.3.1 Hardware and Software Resets ............................................................................ 641
16.3.2 Initialization after Hardware Reset ...................................................................... 644
16.3.3 Transmit Mode .................................................................................................... 649
16.3.4 Receive Mode ...................................................................................................... 655
16.3.5 HCAN Sleep Mode.............................................................................................. 661
16.3.6 HCAN Halt Mode................................................................................................ 663
16.3.7 Interrupt Interface ................................................................................................ 663
16.3.8 DTC Interface ...................................................................................................... 665
17.1.1 Features................................................................................................................ 671
17.1.2 Block Diagram..................................................................................................... 672
17.1.3 Pin Configuration ................................................................................................ 673
17.1.4 Register Configuration......................................................................................... 674
17.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 675
17.2.2 A/D Control/Status Register (ADCSR) ............................................................... 676
17.2.3 A/D Control Register (ADCR) ............................................................................ 679
17.2.4 Module Stop Control Register A (MSTPCRA) ................................................... 680
................................................................................................. 671