h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 486

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 12 Watchdog Timer
12.2.3
Note: * Can only be written with 0 for flag clearing.
RSTCSR is an 8-bit readable/writable * register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal.
RSTCSR is initialized to H'1F by a reset signal from the
reset signal caused by overflows.
Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details
Bit 7—Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from
H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode.
Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the
H8S/2636 if TCNT overflows during watchdog timer operation.
Note: * The modules within the chip are not reset, but TCNT and TCSR within the WDT are reset.
Rev. 6.00 Feb 22, 2005 page 426 of 1484
REJ09B0103-0600
Bit 7
WOVF
0
1
Bit 6
RSTE
0
1
Bit
Initial value :
R/W
see section 12.2.4, Notes on Register Access.
Reset Control/Status Register (RSTCSR)
Description
[Clearing condition]
[Setting condition]
Description
Reset signal is not generated if TCNT overflows *
Reset signal is generated if TCNT overflows
:
:
Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF
Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer
operation
R/(W) *
WOVF
7
0
RSTE
R/W
6
0
RSTS
R/W
5
0
—
—
4
1
R E S
—
—
pin, but not by the WDT internal
3
1
—
—
2
1
—
—
1
1
(Initial value)
(Initial value)
—
—
0
1