h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 790

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 20 RAM
20.2
20.2.1
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in
SYSCR, see section 3.2.2, System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
20.3
When the RAME bit is set to 1, accesses to addresses H'FFE000 to H'FFEFBF (for the H8S/2636),
H'FFB000 to H'FFEFBF (for the H8S/2638, H8S/2639, and H8S/2630), H'FFD800 to H'FFEFBF
(for the H8S/2635 Group), or H'FFFFC0 to H'FFFFFF in the chip are directed to the on-chip
RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed.
Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to
and read in byte or word units. Each type of access can be performed in one state.
Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start
at an even address.
Rev. 6.00 Feb 22, 2005 page 730 of 1484
REJ09B0103-0600
Bit 0
RAME
0
1
Bit
Initial value
R/W
Register Descriptions
System Control Register (SYSCR)
Operation
Description
On-chip RAM is disabled
On-chip RAM is enabled
:
:
:
MACS
R/W
7
0
¾
¾
6
0
INTM1
R/W
5
0
INTM0
R/W
4
0
NMIEG
R/W
3
0
R/W
¾
2
0
¾
¾
1
0
(Initial value)
RAME
R/W
0
1