h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 635

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

[1] Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the
[2] When ICDR is read (dummy data read), reception is started, and the receive clock is output,
[3] The IRIC flag is set to 1 by the following two conditions. At that point, an interrupt request is
[4] Read the IRTR flag in ICSR. If the IRTR flag value is 0, the wait state is cancelled by
[5] If the IRTR flag value is 1, read the ICDR receive data.
[6] Clear the IRTR flag to 0. If condition [3]-1 is true, the master device drives SDA to low level
[7] Set the ACKB bit in ICSR to 1 to set the acknowledge data for the final receive.
[8] Wait for at least 1 clock cycle after the IRIC flag is set to 1 and then wait for the rising edge
[9] Set the TSR bit in ICCR to 1 to switch from the receive mode to the transmit mode. The TSR
[10] Read the ICDR receive data.
[11] Clear the IRTR flag to 0.
[12] The IRIC flag is set to 1 by the following two conditions.
[13] Read the IRTR flag in ICSR. If the IRTR flag value is 0, the wait state is cancelled by
ACKB bit in ICSR to 0 (acknowledge data setting). Clear the IRIC flag to 0, then set the
WAIT bit in ICMR to 1.
and data received, in synchronization with the internal clock.
issued to the CPU if the IEIC bit in ICCR is set to 1.
1. The flag is set at the falling edge of the 8th clock cycle of the receive clock for 1 frame.
2. The flag is set at the rising edge of the 9th clock cycle of the receive clock for 1 frame.
clearing the IRIC flag as described in step [6] below. If the IRTR flag value is 1 and the next
receive data is the final receive data, perform the end processing described in step [7] below.
and returns an acknowledge signal when the receive clock outputs the 9th clock cycle.
Further data can be received by repeating steps [3] through [6].
of the 1st clock cycle of the next receive data.
bit setting value at this point becomes valid when the rising edge of the next 9th clock cycle
is input.
1. The flag is set at the falling edge of the 8th clock cycle of the receive clock for 1 frame.
2. The flag is set at the rising edge of the 9th clock cycle of the receive clock for 1 frame.
clearing the IRIC flag as described in step [14] below. If the IRTR flag value is 1 and the
SCL is automatically held low, in synchronization with the internal clock, until the IRIC
flag is cleared.
The IRIC flag and ICDRF flag are set to 1, indicating that reception of 1 frame of data has
ended. The master device continues to output the receive clock for the receive data.
SCL is automatically held low, in synchronization with the internal clock, until the IRIC
flag is cleared.
The IRIC flag and ICDRF flag are set to 1, indicating that reception of 1 frame of data has
ended. The master device continues to output the receive clock for the receive data.
Section 15 I
2
C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630)
Rev. 6.00 Feb 22, 2005 page 575 of 1484
REJ09B0103-0600