h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 605

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Bit 0—Format Select X (FSX): Used together with the FS bit in SAR to select the
communication format.
The FSX bit also specifies whether or not SARX slave address recognition is performed in slave
mode. For details, see the description of the FS bit in SAR.
15.2.4
ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred
first, performs master mode wait control, and selects the master mode transfer clock frequency and
the transfer bit count. ICMR is assigned to the same address as SAR. ICMR can be written and
read only when the ICE bit is set to 1 in ICCR.
ICMR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—MSB-First/LSB-First Select (MLS): Selects whether data is transferred MSB-first or
LSB-first.
If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and
receive data are stored differently. Transmit data should be written justified toward the MSB side
when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB
side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1.
Do not set this bit to 1 when the I
Bit 7
MLS
0
1
I
Synchronous serial format: non-addressing format without acknowledge bit, for master mode
only
2
C bus format: addressing format with acknowledge bit
Section 15 I
I
2
C Bus Mode Register (ICMR)
Description
MSB-first
LSB-first
2
C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630)
2
C bus format is used.
Rev. 6.00 Feb 22, 2005 page 545 of 1484
REJ09B0103-0600
(Initial value)