peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 82

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Reaching the synchronous state causes a frame alignment recovery interrupt status
ISR2.FAR if enabled. Undisturbed operation starts with the beginning of the next
doubleframe.
4.2.2.3
If the FALC56 detects a remote alarm indication in the received data stream the interrupt
status bit ISR2.RA is set. With setting of bit XSW.XRA a remote alarm (RAI) is sent to
the far end.
By setting FMR2.AXRA the FALC56 automatically transmit the remote alarm bit = 1 in
the outgoing data stream if the receiver detects a loss of frame alignment FRS0.LFA = 1.
If the receiver is in synchronous state FRS0.LFA = 0 the remote alarm bit is reset.
Note: The A-bit can be processed by the system interface. Setting bit TSWM.TRA
4.2.2.4
As an extension for access to the S
is implemented to allow the usage of internal S
doubleframe format.
This function is enabled by setting FMR1.ENSA = 1 for the transmitter and
FMR1.RFS(1:0) = 01 for the receiver. In this case the FALC56 internally works with a 16-
frame structure but no CRC multiframe alignment/generation is performed.
Data Sheet
enables transparency for the A-bit in transmit direction (refer to
A-Bit Access
S
a
-Bit Access
a
-bits through registers RSA(8:4)/XSA(8:4) an option
82
a
-bit registers RSA(8:4)/XSA(8:4) in
Functional Description E1
Table
FALC56 V1.2
PEB 2256
16).
2002-08-27