peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 157

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Figure 52
Note: DR = Dual-Rail interface
5.4.4
The transmit elastic store with a size of max. 2 × 193 bit (two frames) serves as a
temporary store for the PCM data to adapt the system clock (SCLKX) to the internally
generated clock for the transmit data, and to retranslate time slot structure used in the
system to that of the line side. Its optimal start position is initiated when programming the
transmit time slot offset values. A difference in the effective data rates of system side and
transmit side lead to an overflow or underflow of the transmit memory. Thus, errors in
data transmission to the remote end occur. This error condition (transmit slip) is reported
to the microprocessor by interrupt status registers.
The received bit stream from pin XDI is optionally stored in the transmit elastic buffer.
The memory is organized as the receive elastic buffer. Programming of the transmit
buffer size is done by SIC1.XBS1/0:
• XBS1/0 = 00: bypass of the transmit elastic buffer
• XBS1/0 = 01: one frame buffer or 193 bits
Data Sheet
Maximum of wander amplitude (peak-to-peak): (1 UI = 648 ns)
System interface clocking rate: modulo 2.048 MHz:
XL1/
XDOP/
XOID
XL2/
XDON
XCLK
TCLK
(E1: 8MHz)
(T1: 6MHz)
MCLK
DCO-X Digital Controlled Oscillator transmit
Transmit Elastic Buffer (T1/J1)
Transmit Clock System (T1/J1)
DR
DR
Clocking
Unit
D
Pulse Shaper
÷ 4
A
157
E1: 8MHz
T1: 6MHz
Attenuator
Transmit
DCO-X
Jitter
Framer
Functional Description T1/J1
Transmit
Elastic
Store
FALC56 V1.2
Internal Clock of
Receive System
Interface
SCLKR
PEB 2256
2002-08-27
SCLKX
TCLK
RCLK
ITS10305
XDI