peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 401

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Flexible Clock Mode Settings
If flexible master clock mode is used (VFREQ_EN = 1), the according register settings
can be calculated as follows (a windows-based program for automatic calculation is
available, see
the table below.
1. PLL_M and PLL_N must fulfill the equations:
a. 1.5 MHz ≤ f
b. If (a.) is not possible, set MCLK_LOW and fulfill
1.02 MHz ≤ f
c. 65 MHz ≤ f
(as high as possible within this range)
2. Selection of dividing mode to best fulfill:
f
f
Though the target frequency might not be met directly, the dividing mode has to be
selected to reach a frequency, which is as near as possible to the target frequency.
3. Calculation of correction value (frequency mismatch correction)
PHD_E1 = 6 × 4096 × [DIV_E1 - (2 × PLL_N+2)/(PLL_M+1) × (f
PHD_T1 = 6 × 4096 × [DIV_T1 - (2 × PLL_N+2)/(PLL_M+1) × (f
The result of these equations will be in the range of -2048 to +2047. Negative values are
represented in 2s-complement format (e.g. -2000
Table 66
Data Sheet
outE1
outT1
f
MCLK
10.000
12.352
1.544
2.048
8.192
= ( f
= ( f
[MHz]
MCLK
MCLK
MCLK
MCLK
MCLK
× (2 × PLL_N+2) / (PLL_M+1) ) / DIV_E1 (target E1: 16.384 MHz)
× (2 × PLL_N+2) / (PLL_M+1) ) / DIV_T1 (target T1: 12.352 MHz)
Clock Mode Register Settings for E1 or T1/J1
Chapter 13.3
/ (PLL_M+1) ≤ 1.5 MHz
× (2 × PLL_N+2) / (PLL_M+1) ≤ 69.7 MHz
GCM1
/ (PLL_M+1) ≤ 2.048 MHz
F0
00
00
90
F0
H
H
H
H
H
on
GCM2
51
58
58
51
51
page
H
H
H
H
H
481). For some of the standard frequencies see
401
GCM3
D2
D2
00
81
00
H
H
H
H
H
D
= 830
GCM4
C2
C2
8F
80
80
H
; +2000
H
H
H
H
H
MCLK
MCLK
D
GCM5
/12.352 MHz)]
/16.384 MHz)]
= 7D0
00
00
03
04
07
H
H
H
H
H
T1/J1 Registers
FALC56 V1.2
H
).
PEB 2256
2002-08-27
GCM6
15
10
10
10
15
H
H
H
H
H