peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 137

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

FALC56 V1.2
PEB 2256
Functional Description T1/J1
5.1.14.3 CAS Bit-Robbing (T1/J1, serial mode)
The signaling information is carried in the LSB of every sixth frame for each time slot.
The signaling controller samples the bit stream either on the receive line side or if
external signaling is enabled on the receive system side on port RSIG. Receive signaling
data is stored in the registers RS(12:1).
Optionally the complete CAS multiframe is transmitted on pin RSIG (FMR5.EIBR = 1).
The signaling data is clocked out with the working clock of the receive highway (SCLKR)
together with the receive synchronization pulse (SYPR). Data on RSIG is transmitted in
the last 4 bits per time slot and are time slot aligned to the data on RDO. In ESF format
the A,B,C,D bits are placed in the bit positions 5 to 8 per time slot. In F12/72 format the
A and B bits are repeated in the C and D bit positions. The first 4 bits per time slot can
be optionally fixed high or low. The FS/DL time slot is transmitted on RDO and RSIG.
During idle time slots no signaling information is transmitted. Data on RSIG are only valid
if the freeze signaling status is inactive. With FMR2.SAIS all-ones data is transmitted on
RDO and RSIG.
Updating of the received signaling information is controlled by the freeze signaling
status. The freeze signaling status is automatically activated if a loss-of-signal, or a loss-
of-frame-alignment or a receive slip occurs. The current freeze status is output on port
FREEZE (RP(A:D)) and indicated by register SIS.SFS. If SIS.SFS is active updating of
the registers RS(12:1) is disabled. Optionally automatic freeze signaling is disabled by
setting bit SIC3.DAF.
After CAS resynchronization an interrupt is generated. Because at this time the signaling
is still frozen, CAS data is not valid yet. Readout of CAS data has to be delayed until the
next CAS multiframe is received.
5.1.14.4 CAS Bit-Robbing (T1/J1, µP access mode)
The signaling information is carried in the LSB of every sixth frame for each time slot.
Receive data is stored in registers RS(12:1) aligned to the CAS multiframe boundary.
To relieve the µP load from always reading the complete RS(12:1) buffer every 3 ms the
FALC56 notifies the µP by interrupt ISR0.RSC only when signaling changes from one
multiframe to the next. Additionally the FALC56 generates a receive signaling data
change pointer (RSP1/2) which directly points to the updated RS(12:1) register.
Because the CAS controller is working on the PCM highway side of the receive buffer,
slips disturb the CAS data.
5.1.14.5 Bit Oriented Messages in ESF-DL Channel (T1/J1)
The FALC56 HDLC channel 1 supports the DL-channel protocol for ESF format
according to ANSI T1.403 specification or according to AT&T TR54016. The HDLC and
bit oriented message (BOM) receiver are switched on/off independently. If the FALC56
is used for HDLC formats only, the BOM receiver has to be switched off. If HDLC and
Data Sheet
137
2002-08-27