peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 426

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

RAB
HA1, HA0
HFR
Data Sheet
Receive Message Aborted - HDLC Channel 1
This bit is set in SS7 mode, if the maximum number of octets (272+7)
is exceeded. The received frame was aborted from the transmitting
station. According to the HDLC protocol, this frame must be discarded
by the receiver station.
High Byte Address Compare - HDLC Channel 1
Significant only if 2-byte address mode or SS7 mode has been
selected.
In operating modes which provide high byte address recognition, the
FALC56 compares the high byte of a 2-byte address with the contents
of two individually programmable registers (RAH1, RAH2) and the
fixed values FE
Depending on the result of this comparison, the following bit
combinations are possible (SS7 support not active):
00 = RAH2 has been recognized
01 = Broadcast address has been recognized
10 = RAH1 has been recognized C/R = 0 (bit 1)
11 = RAH1 has been recognized C/R = 1 (bit 1)
Note: If RAH1, RAH2 contain identical values, a match is indicated
If Signaling System 7 support is activated (see MODE register), the
bit functions are defined as follows:
00 = not valid
01 = Fill In signaling unit (FISU) detected
10 = Link status signaling unit (LSSU) detected
11 = Message signaling unit (MSU) detected
HDLC Frame Format - HDLC Channel 1
0 =
1 =
Note: Bits RSIS.(7:2) and RSIS.0 are not valid with a BOM frame. This
A BOM frame was received.
A HDLC frame was received.
means, if HFR = 0, all other bits of RSIS have to be ignored
Not valid in SS7 mode. Bit HFR has to be ignored, if SS7 mode
is selected.
by "10" or "11".
H
and FC
426
H
(broadcast address).
T1/J1 Registers
FALC56 V1.2
PEB 2256
2002-08-27