peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 301

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

E-Bit Error Counter (Read)
EBCL
EBCH
EB(15:0)
Data Sheet
EB15
EB7
7
7
E-Bit Errors
If doubleframe format is selected, FEBEH/L has no function. If CRC-
multiframe mode is enabled, FEBEH/L works as submultiframe error
indication counter (16 bits) which counts zeros in S
frame 13 and 15 of every received CRC multiframe. The error counter
does not roll over.
During alarm simulation, the counter is incremented once per
submultiframe up to its saturation.
Clearing and updating the counter is done according to bit
FMR1.ECM.
If this bit is reset the error counter is permanently updated in the
buffer. For correct read access of the error counter bit DEC.DEBC
has to be set. With the rising edge of this bit updating the buffer is
stopped and the error counter is reset. Bit DEC.DEBC is reset
automatically with reading the error counter high byte.
If FMR1.ECM is set every second (interrupt ISR3.SEC) the error
counter is latched and then automatically reset. The latched error
counter state should be read within the next second.
301
FALC56 V1.2
i
EB0
EB8
-bit position of
E1 Registers
0
0
PEB 2256
2002-08-27
(56)
(57)