peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 298

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Framing Error Counter (Read)
FECL
FECH
FE(15:0)
Data Sheet
FE15
FE7
7
7
Framing Errors
This 16-bit counter is incremented when a FAS word has been
received with an error.
Framing errors are counted during basic frame synchronous state
only (but even if multiframe synchronous state is not reached yet).
During alarm simulation, the counter is incremented every 250 µ s up
to its saturation. The error counter does not roll over.
Clearing and updating the counter is done according to bit
FMR1.ECM.
If this bit is reset the error counter is permanently updated in the
buffer. For correct read access of the error counter bit DEC.DFEC has
to be set. With the rising edge of this bit updating the buffer is stopped
and the error counter is reset. Bit DEC.DFEC is reset automatically
with reading the error counter high byte.
If FMR1.ECM is set every second (interrupt ISR3.SEC) the error
counter is latched and then automatically reset. The latched error
counter state should be read within the next second.
298
FALC56 V1.2
FE0
FE8
E1 Registers
0
0
PEB 2256
2002-08-27
(50)
(51)