peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 30

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Table 1
Pin
No.
51
52
53
12
Data Sheet
Ball
No.
E9
E7
D7
E3
Pin Definitions - Microprocessor Interface (cont’d)
Symbol
ALE
RD/DS
WR/RW
DBW
Output (O)
Supply (S)
I + PU
I + PU
I + PU
Input (I)
I + PU
Function
Address Latch Enable
A high on this line indicates an address on an
external multiplexed address/data bus. The
address information provided on lines A(7:0) is
internally latched with the falling edge of ALE.
This function allows the FALC
connected to a multiplexed address/data bus
without the need for external latches. In this
case, pins A(7:0) must be connected to the
data bus pins externally. In case of
demultiplexed mode this pin can be connected
directly to
Read Enable (Intel bus mode)
This signal indicates a read operation. When
the FALC
enables the bus drivers to output data from an
internal register addressed by A(7:0) to the
Data Bus.
Data Strobe (Motorola bus mode)
This pin serves as input to control read/write
operations.
WRite Enable (Intel bus mode)
This signal indicates a write operation. When
CS is active the FALC
register with data provided on the data bus.
Read/Write Enable (Motorola bus mode)
This signal distinguishes between read and
write operation.
Data Bus Width (Bus interface mode)
A low signal on this input selects the 8-bit bus
interface mode. A high signal on this input
selects the 16-bit bus interface mode. In this
case word transfer to/from the internal
registers is enabled. Byte transfers are
implemented by using A0 and BHE/BLE.
30
®
V
56 is selected via CS, the RD signal
DD
or can be left open.
®
56 loads an internal
Pin Descriptions
®
56 to be
FALC56 V1.2
PEB 2256
2002-08-27