peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 312

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

CRC4
SA6SC
RPF
Interrupt Status Register 1 (Read)
ISR1
All bits are reset when ISR1 is read.
If bit GCR.VIS is set, interrupt statuses in ISR1 are flagged although they are masked by
register IMR1. However, these masked interrupt statuses neither generate a signal on
INT, nor are visible in register GIS.
LLBSC
Data Sheet
LLBSC
7
Receive CRC4 Error
0 =
1 =
Receive S
With every change of state of the received S
interrupt is set.
Receive Pool Full
32 bytes of a frame have arrived in the receive FIFO. The frame is not
yet completely received.
Line Loop-Back Status Change
Depending on bit LCR1.EPRM the source of this interrupt status
changed:
LCR1.EPRM = 0: This bit is set, if the LLB activate signal or the LLB
deactivate signal, respectively, is detected over a period of 25 ms with
a bit error rate less than 10
The LLBSC bit is also set, if the current detection status is left, i.e., if
the bit error rate exceeds 10
The actual detection status can be read from the RSP.LLBAD and
RSP.LLBDD, respectively.
PRBS Status Change
LCR1.EPRM = 1: With any change of state of the PRBS synchronizer
this bit is set. The current status of the PRBS synchronizer is
indicated in RSP.LLBAD.
RDO
No CRC4 error occurs.
The CRC4 check of the last received submultiframe failed.
ALLS
a
6-Bit Status Changed
XDU
312
-2
XMB
-2
.
.
SUEX
XLSC
a
6-bit combinations this
FALC56 V1.2
XPR
E1 Registers
0
PEB 2256
2002-08-27
(69)