peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 38

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Table 3
Pin
No.
75
Data Sheet
Pin
No.
A3
Pin Definitions - Clock Generation (cont’d)
Symbol
RCLK
Output (O)
Supply (S)
O + PU
Input (I)
Function
Receive Clock
After reset this port is configured to be
internally pulled up weakly. Setting of bit
PC5.CRP switches this port to be an active
output.
CMR1.RS(1:0) = 00:
Receive clock extracted from the incoming
data pulses. The clock frequency is 2.048 MHz
(E1) or 1.544 MHz (T1/J1). In case of Loss-Of-
Signal (LOS) the RCLK is derived from the
clock that is provided on MCLK.
CMR1.RS(1:0) = 01:
Receive clock extracted from the incoming
data pulses. The clock frequency is 2.048 MHz
(E1) or 1.544 MHz (T1/J1). RCLK remains high
in case of LOS (indicated by FRS0.LOS = 1).
CMR1.RS(1:0) = 10:
Dejittered clock generated by the internal
DCO-R circuit. The clock frequency is
2.048 MHz (E1 or T1/J1 and SIC2.SSC2 = 0)
or 1.544 MHz (T1/J1 and SIC2.SSC2 = 1).
CMR1.RS(1:0) = 11:
Dejittered clock generated by the internal
DCO-R circuit. The clock frequency is
8.192 MHz (E1 or T1/J1 and SIC2.SSC2 = 0)
or 6.176 MHz (T1/J1 and SIC2.SSC2 = 1).
38
Pin Descriptions
FALC56 V1.2
PEB 2256
2002-08-27