peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 183

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

5.6.3
To perform an effective circuit test a line loop is implemented.
If the payload loop-back (FMR2.PLB) is activated the received 192 bits of payload data
is looped back to the transmit direction. The framing bits, CRC6 and DL-bits are not
looped, if FMR4.TM = 0. They are originated by the FALC56 transmitter. If FMR4.TM = 1
the received FS/DL-bit is sent transparently back to the line interface. Following pins are
ignored: XDI, XSIG, TCLK, SCLKX, SYPX and XMFS. All the received data is processed
normally. With bit FMR2.SAIS an AIS can be sent to the system interface on pin RDO.
Figure 73
Data Sheet
RL1
RL2
XL1
XL2
Payload Loop-Back
Payload Loop (T1/J1)
Clock +
Data
Recovery
Trans.
Framer
RCLK
Rec.
Framer
183
Elast.
Store
Elast.
Store
Functional Description T1/J1
AIS-GEN
MUX
FALC56 V1.2
PEB 2256
2002-08-27
ITS09748
RDO
SCLKR
XDI
SCLKX